Scaling of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. Continuing the scaling of MOSFETs results in severe degradation of carrier mobility, however, which in turn adversely affects the device drive current. To further enhance the performance of MOS devices, carrier mobility enhancement becomes a key element in developing next generation technologies. Among efforts to improve carrier mobility, introducing stress into the channel region of MOS devices is widely adopted. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (“PMOS”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is growing SiGe stressors in the source and drain regions of the respective PMOS devices. Such a method typically includes the steps of forming recesses in a silicon substrate along edges of gate spacers, epitaxially growing SiGe stressors in the recesses, and annealing. Since SiGe has a greater lattice constant than the silicon substrate does, after annealing, it expands and applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor.
The above-discussed method, however, suffers drawbacks when used for the formation of static random access memory (SRAM) cells. FIG. 1 illustrates an exemplary circuit diagram of a six-transistor SRAM cell, which includes pass-gate transistors PG1 and PG2, pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2. Gates 2 and 4 of the respective pass-gate transistors PG1 and PG2 are controlled by a word-line WL that determines whether the current SRAM cell is selected or not. A latch formed of pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD2 stores a state. The stored state can be read or written through a bit line BL.
Conventionally, on a memory chip, PMOS devices in both peripheral circuits and memory circuits are formed with SiGe stressors, which causes significant improvement in the drive currents of the pull-up PMOS devices in SRAM cells. The drive currents of pull-down NMOS devices, however, are difficult to improve, and thus have relatively smaller drive currents. The unbalanced performance of PMOS and NMOS devices causes a writing problem. For example, when a “0” is written into the memory cell, the pull-up transistor PU2 has a high drive current, hence a high ability for supplying charges from Vcc to node 6. Conversely, NMOS device PD2 has a relatively low drive current, hence a low ability for discharging charges from node 6 to Vss. Consequently, it takes a long period of time to write the state “0” Additionally, write margins of the SRAM cells are degraded due to the high drive currents of PMOS devices. A low write margin results in an increased possibility of erroneous writing. For high performance SRAM cells, read and write operations are preferably balanced. Therefore, it is preferred that the drive currents of pull-up PMOS devices in SRAM cells be controlled.
The above-discussed problems have also been found in the design of inverters. A typical inverter includes a PMOS device serially connected to an NMOS device. In order to quickly change the output voltage between a high voltage and a low voltage, it is also preferred that the drive current of the PMOS device be controlled.
The approaches for reducing the drive currents of PMOS devices include increasing the gate lengths of PMOS devices and increasing pocket/channel implantation dosages. However, when technologies evolve into 65 nm or lower, there is very little room for increasing the gate lengths, and the resulting reductions in drive currents of PMOS devices are not adequate to compensate for the increase in drive currents due to the formation of SiGe stressors. Increasing pocket/channel implantation dosages can also reduce device drive currents. However, the leakage currents are increased with the increase in the doping concentration adjacent the channel regions. Therefore, the ability to increase the gate lengths of PMOS devices and to increase the pocket/channel implantation dosages is limited.
A possible solution for such a problem is to form SiGe stressors for PMOS devices in the peripheral circuit, but not for the pull-up PMOS devices in SRAM cells. Such a solution is not preferred, however, since the peripheral circuit typically occupies a small region on a memory chip, and thus SiGe stressors will only be formed in a small region, resulting in pattern loading effects and process difficulties for subsequent process steps.